100825/tex/quine3dnf100425.txt

(C) David Vajda
Sat Oct  4 13:47:22 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		0
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1


 	x2	x1	x0		y
 2	0	1	0		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1


  	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
Gruppe 2:
 5	1	0	1		1
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1


2:6			-	1	0
5:7			1	-	1
6:7			1	1	-


		2	5	6	7
2:6		+		+
5:7			+		+
6:7				+	+


		2	5	6	7
2:6		+		+
5:7			+		+


2:6			-	1	0
5:7			1	-	1

ok,

	y	<=	(x1 and not x0) or
			(x2 and x0);


-- (C) David Vajda
-- Sat Oct  4 13:47:22 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine3dnf100425 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine3dnf100425 is
begin
	y	<=	(x1 and not x0) or
			(x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3dnf100425testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine3dnf100425testbench is
	component quine3dnf100425
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine3dnf100425 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);