GAL16V8
RIPPLECARRYCHAINADDER20250920DAVIDVAJDA
DECLARATIONS
// inputs
clk pin 11; // clock signal
en pin 9; // enable signal to start the traffic light
// nodes
q0 node istype 'reg';
q1 node istype 'reg';
// output
red pin 36 istype 'com'; // the red light
yellow pin 42 istype 'com'; // the yellow light
green pin 39 istype 'com'; // the green light
EQUATIONS
q0 := !q0 & !en;
q1 := (q1 $ q0) & !en;
q0.clk = clk;
q1.clk = clk;
red = q1;
yellow = !q0;
green = !(q1 & !q0);
TEST_VECTORS
([clk, en] -> [ red, yellow, green]);
@repeat 1 {[.C., 1] -> [.X., .X., .X.];}
@repeat 7 {[.C., 0] -> [.X., .X., .X.];}
@repeat 3 {[.C., 1] -> [.X., .X., .X.];}
@repeat 40 {[.C., 0] -> [.X., .X., .X.];}
END