Nächste Seite: 20250924 Aufwärts: trixie13ofmyexcersize Vorherige Seite: 20250920
1.) Rechne die Zahl in binaer Darstellung in eine Dezimale Darstellung um
0101000001000011b 20547d
2.) Rechne die Zahl in dezimal darstellung in eine Binaerdarstellung um
23549 0101101111111101
3.) Addiere die drei Zahlen schriftlich
19332
+ 39822
+ 27191
-----------------
86345
4.) Subtrahiere die letzten drei Zahlen schriftlich von der ersten schriftlich
32036
- 8625
- 6388
- 12983
-----------------
4040
5.) Rechne die Zahl ins zweier komplement um, mit 8 Bit - und subtrahiere diese zahl von der ersten und rechne das Ergebnis nach dezimal
52 -14 = 38
00110100 11110010 = 00100110
6.) Multipliziere die zwei Zahlen schriftlich
48875*45420 = 2219902500
7.) Dividiere die zwei Zahlen schriftlich
4072/35361 = 0
8.) Errechne x Logarithmisch mit dem Taschenrechner
38035^x = 662990462
9.) Errechne mit dem Abakus
8 + 61 + 95 + 15 + 81 + 75 + 19 + 1 + 27 + 70
10.) Errechne mit dem Abakus
827 + 3590 + 362 + 6298 + 7019 + 3249 + 433 + 5811 + 3639 + 5889
Python 3.11.2 (main, Apr 28 2025, 14:11:48) [GCC 12.2.0] on linux Type "help", "copyright", "credits" or "license()" for more information. >>> ====================== RESTART: /home/david/py20250923.py ====================== hello world >>> ====================== RESTART: /home/david/py20250923.py ====================== hello world you have entered take care not to encounter the man with the troughs! much fun! moral level 2.0 ok
# (C) David Vajda
# 09/23/25
# excersize python 3
print ("hello world")
print ("you have entered")
print ("take care not to encounter the man with the troughs!")
print ("much fun!")
print ("moral level 2.0")
print ("ok")
n = 5
m = 1
while n > 0:
m = m * n
n = n - 1;
print (m)
print ("this was the faculty!")
print ("ok next order: go and watch arround - don't care about this or watch this channel, never try to interact!")
print ("let's have std. additions")
x = 5 + 7
y = x + 4.3 + 3.14
x1 = x/2 * 50000
x2 = 4 + 4 + 6
print (x)
print (y)
print (x1)
print (x2)
print ((x+y)/x1+x2)
print ("this is text input excersize nr.1")
x = int(input ())
Zero = 0
print ("you have decided this way", x)
if x % 10 == Zero:
print ("i can't see what you meen but you have decided like human calculated in decimals!")
else:
print ("we will see")
GAL16V8
-------\___/-------
/OE | 1 20 | VCC
| |
X2 | 2 19 | NC
| |
X1 | 3 18 | NC
| |
X0 | 4 17 | NC
| |
NC | 5 16 | NC
| |
NC | 6 15 | NC
| |
NC | 7 14 | NC
| |
NC | 8 13 | NC
| |
NC | 9 12 | Y
| |
GND | 10 11 | CLK
-------------------
Pin 19 = NC XOR = 0 AC1 = 0 0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 6 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 7 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 18 = NC XOR = 0 AC1 = 0 8 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 9 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 10 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 11 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 12 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 13 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 14 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 15 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 17 = NC XOR = 0 AC1 = 0 16 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 17 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 18 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 19 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 20 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 21 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 22 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 23 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 16 = NC XOR = 0 AC1 = 0 24 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 25 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 26 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 27 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 28 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 29 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 30 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 31 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 15 = NC XOR = 0 AC1 = 0 32 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 33 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 34 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 35 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 36 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 37 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 38 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 39 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 14 = NC XOR = 0 AC1 = 0 40 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 41 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 42 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 43 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 44 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 45 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 46 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 47 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 13 = NC XOR = 0 AC1 = 0 48 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 49 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 50 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 51 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 52 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 53 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 54 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 55 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Pin 12 = Y XOR = 1 AC1 = 0 56 -x-- -x-- ---- ---- ---- ---- ---- ---- 57 x--- x--- ---- ---- ---- ---- ---- ---- 58 ---- -x-- x--- ---- ---- ---- ---- ---- 59 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 60 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 61 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 62 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 63 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
GAL16V8
QUINE 3 NETWORK DNF 09/23/25
/OE X2 X1 X0 NC NC NC NC NC GND
CLK Y NC NC NC NC NC NC NC VCC
Y = !X2 * !X1 + X2 * X1 + !X1 * X0;
DESCRIPTION
QUINE 3 NETWORK DNF 23/09/2025
Used Program: GALasm 2.1 GAL-Assembler: GALasm 2.1 Device: GAL16V8 *F0 *G0 *QF2194 *L1792 10111011111111111111111111111111 *L1824 01110111111111111111111111111111 *L1856 11111011011111111111111111111111 *L2048 00000001 *L2056 0101000101010101010010010100111001000101001000000011001100100000 *L2120 00000000 *L2128 1111111111111111111111111111111111111111111111111111111111111111 *L2192 1 *L2193 0 *C17c7 * 5502
Pin # | Name | Pin Type ----------------------------- 1 | /OE | Input 2 | X2 | Input 3 | X1 | Input 4 | X0 | Input 5 | NC | Input 6 | NC | Input 7 | NC | Input 8 | NC | Input 9 | NC | Input 10 | GND | GND 11 | CLK | Input 12 | Y | Output 13 | NC | NC 14 | NC | NC 15 | NC | NC 16 | NC | NC 17 | NC | NC 18 | NC | NC 19 | NC | NC 20 | VCC | VCC
Timing Analyzer Settings
Time_Scale: 1.000000E-15
Time_Per_Division: 8.000000E+06
NumberDivisions: 10
Start_Time: 0.0
End_Time: 80000000.0
Digital_Signal
Position: 1
Height: 24
Space_Above: 24
Name: x0
Start_State: 0
Number_Edges: 8
Rise_Time: 0.2
Fall_Time: 0.2
Edge: 10000000.0 1
Edge: 20000000.0 0
Edge: 30000000.0 1
Edge: 40000000.0 0
Edge: 50000000.0 1
Edge: 60000000.0 0
Edge: 70000000.0 1
Edge: 80000000.0 0
Digital_Signal
Position: 2
Height: 24
Space_Above: 24
Name: x1
Start_State: 0
Number_Edges: 4
Rise_Time: 0.2
Fall_Time: 0.2
Edge: 20000000.0 1
Edge: 40000000.0 0
Edge: 60000000.0 1
Edge: 80000000.0 0
Digital_Signal
Position: 3
Height: 24
Space_Above: 24
Name: x2
Start_State: 0
Number_Edges: 2
Rise_Time: 0.2
Fall_Time: 0.2
Edge: 40000000.0 1
Edge: 80000000.0 0
Digital_Signal
Position: 4
Height: 24
Space_Above: 24
Name: y
Start_State: 1
Number_Edges: 2
Rise_Time: 0.2
Fall_Time: 0.2
Edge: 20000000.0 0
Edge: 50000000.0 1
(C) David Vajda Tue Sep 23 11:22:50 2025 3 Network - TTL - Disjunktive Normalform x2 x1 x0 y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 x2 x1 x0 y 0 0 0 0 1 1 0 0 1 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 x2 x1 x0 y Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 0:1 0 0 - 1:5 - 0 1 6:7 1 1 - 0:1 0 0 - 6:7 1 1 - 1:5 - 0 1 Gruppe 0: 0:1 0 0 - Gruppe 2: 6:7 1 1 - Gruppe 1: 1:5 - 0 1 0 1 5 6 7 0:1 + + 6:7 + + 1:5 + + 0:1 0 0 - 6:7 1 1 - 1:5 - 0 1 y <= (not x2 and not x1) or (x2 and x1) or (not x1 and x0); -- (C) David Vajda -- Tue Sep 23 11:22:50 2025 -- 3 Network - TTL - Disjunktive Normalform library ieee; use ieee.std_logic_1164.all; entity quine20250923 is port ( x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine20250923 is begin y <= (not x2 and not x1) or (x2 and x1) or (not x1 and x0); end; library ieee; use ieee.std_logic_1164.all; entity quine20250923testbench is port ( y: out std_logic ); end; architecture behaviour of quine20250923testbench is component quine20250923 port ( x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x2, x1, x0: std_logic; begin q: quine20250923 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
$date Tue Sep 23 11:41:49 2025 $end $version GTKWave Analyzer v3.3.118 (w)1999-2023 BSI $end $timescale 1fs $end $scope module top $end $scope module quine20250923testbench $end $var 1 % y $end $var 1 $ x2 $end $var 1 # x1 $end $var 1 " x0 $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars 0" 0$ 0# 1% $end #10000000 1" #20000000 0" 0% 1# #30000000 1" #40000000 0" 0# 1$ #50000000 1" 1% #60000000 1# 0" #70000000 1" #80000000 0" 0$ 0#
-- (C) David Vajda -- Tue Sep 23 11:22:50 2025 -- 3 Network - TTL - Disjunktive Normalform library ieee; use ieee.std_logic_1164.all; entity quine20250923 is port ( x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine20250923 is begin y <= (not x2 and not x1) or (x2 and x1) or (not x1 and x0); end; library ieee; use ieee.std_logic_1164.all; entity quine20250923testbench is port ( y: out std_logic ); end; architecture behaviour of quine20250923testbench is component quine20250923 port ( x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x2, x1, x0: std_logic; begin q: quine20250923 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
-- (C) David Vajda -- Tue Sep 23 11:22:50 2025 -- 3 Network - TTL - Disjunktive Normalform library ieee; use ieee.std_logic_1164.all; entity quine20250923 is port ( x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine20250923 is begin y <= (not x2 and not x1) or (x2 and x1) or (not x1 and x0); end; library ieee; use ieee.std_logic_1164.all; entity quine20250923testbench is port ( y: out std_logic ); end; architecture behaviour of quine20250923testbench is component quine20250923 port ( x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x2, x1, x0: std_logic; begin q: quine20250923 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y); x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns; x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; end;
