D-Latch in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241121 is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch20241121 is
begin
    q <= r nor p;
    p <= s nor q;
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch20241121 is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch20241121 is
    component rslatch20241121
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal d, e: std_logic;
begin
    rs: rslatch20241121 PORT MAP (s=>d, r=>e, q=>q);
    d <= s and c;
    e <= r and c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20241121 is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch20241121 is
    component clktriggeredrslatch20241121
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch20241121 PORT MAP (r=>e, s=>f, c=>c, q=>q);
    e <= not d;
    f <= d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20241121testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatch20241121testbench is
    component dlatch20241121
    port (
        d: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dlatch: dlatch20241121 PORT MAP (d=>d, c=>c, q=>q);

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;